Leakage Current And Dynamic Power Analysis Of Finfet Based 7t Sram At 45nm Technology

As technology is scaled down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 45nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable-supply voltage schemes. It is well known that leakage savings using transistor stacks is not effective in double-gate technologies such as FinFETs, due to the absence of body effect. However, transistor stacking along with variable supply voltage operation of FinFETs can offer larger leakage savings compared to that of bulk devices. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. Furthermore, 2:4 decoder has been designed and results obtained through proposed model have been verified. For the validation of our design approach, output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.